1. Field of the Invention
The present invention relates to an AlInAs/GaInAs heterostructure confinement bipolar transistor, and especially relates to an AlInAs/GaInAs heterostructure confinement bipolar transistor which inserts an n GaInAs emitter layer to remove emitter-base potential spike and to lower offset voltage.
2. Description of the Related Art
Recently, in microwave, high-speed and high-power applications, hetero-junction bipolar transistors (HBT) have attracted much attention.
A substrate of InP material is suitable for integrated circuits. HBT with a base of GaInAs material is widely applied in many fields, for example, in a field for reducing transient time. A low surface-combination rate can effectively reduce base surface combination current and offset voltage, and increase current gain.
But, an AlInAs/GaInAs HBT has a large conduction band discontinuity (.delta.Ec), e.g., 0.55 eV, at AlInAs/GaInAs junction. If a potential spike exists at a base-emitter junction, the emitter injection efficiency is eliminated to reduce output current and current gain in small current region. This characteristic is not suitable for high-current applications. In addition, if an offset voltage has occurred at an emitter-collector junction, the power consumption is increased, and the circuit applications are eliminated.
In the prior art, there are two methods to reduce offset voltage. The first is to use a graded composition at an E-B junction. The second is to insert n GaAs at an E-B junction. That is, a hetero-structure emitter bipolar transistor (HEBT) is performed. But these methods still have their disadvantages and difficulties. As to the first prior art, a precise composition is hard to achieve, and a graded compositioned at an E-B junction is not suitable for GaInAs/GaAs or AlInAs/GaInAs material. As to the second prior art, inserting n GaAs material at an E-B junction leads to a charge storage and reduces current gain.